1. Field of the Invention
The present invention relates to a method for fabricating semiconductor memory devices, and more specifically, to a method for fabricating read-only-memory (ROM) devices with self-aligned code implants.
2. Description of the Prior Art
Semiconductor ROM devices are generally composed of a plurality of memory cells which are formed by intersecting a number of bit lines and word lines on semiconductor substrates. Since each memory cell of the ROM device corresponds to a transistor, its on/off states can be well-controlled by properly adjusting the dopant concentration of the transistor's channel region. That is, the ROM devices are programmed through a specific arrangement of code diffusion regions in the semiconductor substrates, thus deciding the conducting states of the channel regions and the on/off states of the memory cells. These will be described in detail as follows.
In general, the code diffusion regions are formed by implanting ions into the semiconductor substrates through code masks, thus the name "mask ROM." A conventional manufacturing process for a mask ROM device will now be described in accompaniment with the cross-sectional views of FIG. 1 through FIG. 3. In the present example, the ROM device is fabricated on a silicon substrate having a P-type conductivity, that is, each memory cell is an N-type transistor.
First referring to FIG. 1, a gate oxide layer 13 and a polysilicon layer 15 are subsequently formed over silicon substrate 11. Since polysilicon layer 15 contains impurities, it has high conductivity and is provided for the word lines of the ROM device. Therefore, through a photolithography step and an etching step, polysilicon layer 15 is patterned into a plurality of word lines 16, as is depicted in FIG. 2.
It is noted that the structure of FIG. 2 may be subjected to an ion implantation step to form a plurality of bit lines in the substrate before the formation of word lines 16. Since the cross-sectional views of FIG. 1 through FIG. 3 are taken along the channel regions of the memory cells, the bit lines are not shown in the figures.
Further referring to FIG. 3, another photolithography step is performed to form a photoresist layer 17 as a code implant mask over the structure of FIG. 2. Photoresist layer 17 covers all memory cells but the channel regions of off-state memory cells. Then through code implant windows 18 defined by photoresist layer 17, P-type ions, such as boron ions, are implanted into the exposed channel regions of the memory cells to form code diffusion regions 19 in substrate 11.
The aforementioned ROM device operates by changing the voltage of word lines 16 between a high level and a low Level. For the "on"-cells, when the voltage of word lines 16 is at a high level, the channel regions beneath the word lines in the substrate will be turned on and current flow through the bit lines will be sensed. The "off"-cells have code diffusion regions 19, giving their channel regions a higher dopant concentration than that of the "on"-cells, so they need a higher threshold voltage to turn on the channels. That is, unless the high level voltage of the word lines increases, the memory cells having the code diffusion regions in their channel regions will maintain in the "off" state. Therefore, the ROM device can be programmed to contain both the "on"- and "off"-cells as desired.
However, the above-mentioned code implant process will result in impurity diffusion. Since the code implant mask, i.e., photoresist layer 17 in FIG. 3, may shift away through mis-alignment in the photolithography step, code diffusion regions 19 in substrate 11 will also shift away. With the shrinkage of the ROM device, if code diffusion regions 19 are not in their intended location, they will be very close to the channel regions of other memory cells. Since boron ions have a high diffusion coefficient, and they are generally utilized for code implantation as stated above, they will probably diffuse to the channel regions of any nearby memory cells, changing the dopant concentration therein. Therefore, an original "on"-cell may fail to turn on, thus becoming an "off"-cell due to the diffusion of boron ions.
The programming errors caused by the mis-alignment of the code mask and diffusion of impurities will become more serious as the dimension of the semiconductor device decreases. Therefore, the yield of the ROM memory devices can not be improved without modifying the conventional code implant process.